A read only memory (ROM) structure comprises a matrix of intersecting bit lines and word lines with memory cells at select intersections. The structure is typically operated in one of two different modes: pre-charge and read. The need to pre-charge bit lines prior to a read operation causes much of the power consumption of the structure, due to charging of the bit lines themselves, as well as the power consumed by the pre-charging circuit which has to toggle through charge cycles whenever there is a read operation. FIG. 1 shows a simple prior art ROM structure 100 comprising a matrix of bit lines 102 and word lines 104 having memory cells in the form of NMOS transistors 106 at certain cross-over points, thereby defining a structure with a predefined code “written” into it. A pre-charge circuit comprising PMOS transistors 108 is shown, which provides a PMOS transistor 108 for each bit line to allow each bit line 102 to be pre-charged to VDD prior to a read operation. A logic low pre-charge signal PRCH is applied to the gates of the PMOS transistors 108 to cause current to pass up through the bit lines, thereby charging the bit lines 102 prior to a read operation. During this pre-charge mode, the word lines 104 are kept low to switch off the transistors 106, thereby charging the bit lines 102. During a read operation, one of the intersections is selected by selecting a word line (word line goes high) and selecting a bit line by means of the switches 110. In addition, the PRCH signal goes high. By having a high on the selected word line 104, the transistors 106 on that word line are switched on. If the chosen intersection between that word line and the selected bit line 108 has a NMOS transistor 106, the selected bit line 102 has a current path to ground through the transistor 106. This causes any current on the selected bit line to flow through the bit line to ground, allowing the current to be detected by the sense amplifier 112. Thus, if the selected intersection in the matrix includes a memory cell (NMOS transistor 106), current flow is detected. However, it will be appreciated that all of the other bit lines with memory cells on the selected word line will also discharge to ground. These all have to be pre-charged prior to the next read operation, causing considerable power to be consumed. Furthermore, during static mode, the bit lines are high and word lines are low, thus resulting in considerable DC leakage, corresponding to the number of transistors 106.
One proposed solution has been to provide for a pre-discharging of the bit lines instead of a pre-charging. In such a solution, as shown in FIG. 2, there is a special pre-discharge circuit 202 with NMOS transistors 204 which provide a current path to ground when switched on by pre-discharge signal (PRDCHG) 208 which controls all pre-discharge transistors in the pre-discharge circuit 202. During pre-discharge mode all word lines 206 are low and PRDCHG signal 208 is high. This allows all bit lines 210 to discharge through transistors 204. During a read operation, one of the word lines 206 is selected by going high and one of the bit lines 210 is selected by means of multiplexer switches 212. Also, the transistors of the pre-discharge circuit 202 are switched off. Thus, for example, if one wanted to read bit line 214 (BL0), all pre-discharge transistors 204 would be closed (non-conducting), and current supplied by the sense amplifier circuit 220 would flow up through the selected bit line 214 to ground via the selected transistor 206. Thus, there is no unnecessary charging and discharging of bit lines. However, there is still substantial power consumption involved in toggling the transistors 204 of the pre-discharge circuit 202 due to charging of the transistors 204 even when they are not being selected during a read operation. Thus there is a substantial load provided to the PRDCHG signal 208 by the string of transistors 204.
The present invention seeks to provide a lower power consumption solution.